1. Field of the Invention
The present invention relates to a solid-state image sensor and in particular to an output block of a solid-state image sensor.
2. Description of the Related Art
FIG. 9 is a circuit diagram equivalent to a source follower amplifier provided on a single chip in a conventional typical solid-state image sensor. As shown in FIG. 9, in the single-chip source follower amplifier of the conventional solid-state image sensor, a back gate is electrically open with respect to a driver transistor source.
Japanese Patent Publication (Unexamined) No. A-60-223161 [1] discloses means for enhancing the gain of the single-chip source follower amplifier for such a conventional solid-state image sensor output block.
FIG. 10A is a cross sectional view of a solid-state image sensor disclosed in the aforementioned Document [1], and FIG. 10B shows a circuit equivalent to a single-chip source follower amplifier of the solid-state image sensor.
As shown in FIG. 10B, components of the solid-state image sensor excluding a driver transistor 4 are formed in a first reverse-conductive region 17 having a reverse conductivity with respect to a semiconductor substrate 11 having a first conductivity, whereas the driver transistor 4 is formed in a second reverse-conductive region 18 which is independent from the first reverse-conductive region. Furthermore, the second reverse-conductive region 18 is connected to a source 19 of the driver transistor 4.
If it is assumed that the driver transistor has an interactive conductance gm, the back gate (second reverse-conductive region 18) has a conductance gmb, the driver transistor has an output conductance gds1, and the load transistor has an output conductance gds2, then the source follower amplifier has a gain G which can be expressed by equation (1) as follows. EQU G=gm/(gm+gmb+bds1+gds2) (1)
Therefore, if the back gate is connected to the source of the driver transistor, then gmb=0, enabling to increase the gain G.
In addition to the disclosure in Document [1], various techniques have been suggested as the solid-state image sensor output method.
For example, Japanese Patent Publication (Unexamined) No. A-5-191735 [2] discloses a CCD type solid-state image sensor in which a source voltage obtained by providing a self-bias resistor in a load MOS FET of a source follower circuit is feedback-ed via a feedback amplifier to a gate of the load MOS FET so as to increase the gain.
Japanese Patent Publication (Unexamined) No. A-7-273568 [3] discloses a voltage circuit including a MOS transistor having a back gate and a source which are independent from each other so as to obtain a high impedance between them, thus enabling to eliminate affects from a parasitic capacitance as well as to drive with the back gate potential and source potential at an identical value so as to eliminate the substrate bias effect.
However, in the solid-state image sensor (see FIG. 10) disclosed in Document [1], the semiconductor substrate 11 is N type, and the reverse-conductive regions 17 and 18 are P type. Moreover, a source voltage 2 of the source follower amplifier is 15 V. Accordingly, a voltage in the order of about 15 V has been applied to the semiconductor substrate 11. However, with the tendency to reduce the voltage, currently a voltage in the order of about 5 V is applied. It should be noted that the first reverse-conductive region 17 has a potential 0V, whereas the second reverse-conductive region 18 connected to the driver transistor source 19 has a potential of about 8 V.
There is no problem while 15 V is applied to the semiconductor substrate 11. However, when a voltage applied to the semiconductor substrate 11 is in the order of 5 V, the P-type second reverse-conductive region 18 and the N-type semiconductor substrate 11 constitute a forward bias, disabling the operation as the solid-state image sensor.
Moreover, the second reverse-conductive region 18 is formed to be isolated from the first reverse-conductive regions 17. This results in a large area of the driver transistor portion, which is a disadvantage in reducing the size and weight of the solid-state image sensor.
Moreover, in the solid-state image sensor disclosed in Document [3], it is necessary to reverse an output for feedback to the gate. For this, it is necessary to provide an output reversing circuit, complicating the configuration of the solid-state image sensor.
Moreover, in the voltage circuit disclosed in Document [3], when applying a voltage to a back gate on a single chip, the back gate need be electrically isolated from the other back gate. Thus, the voltage circuit disclosed here has a problem that the transistor need to have a large area for applying a voltage to the back gate.